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Espressif Systems /ESP32-S3 /SPI1 /CACHE_FCTRL

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Interpret as CACHE_FCTRL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (CACHE_USR_CMD_4BYTE)CACHE_USR_CMD_4BYTE 0 (FDIN_DUAL)FDIN_DUAL 0 (FDOUT_DUAL)FDOUT_DUAL 0 (FADDR_DUAL)FADDR_DUAL 0 (FDIN_QUAD)FDIN_QUAD 0 (FDOUT_QUAD)FDOUT_QUAD 0 (FADDR_QUAD)FADDR_QUAD

Description

SPI1 bit mode control register.

Fields

CACHE_USR_CMD_4BYTE

Set this bit to enable SPI1 transfer with 32 bits address. The value of SPI_MEM_USR_ADDR_BITLEN should be 31.
FDIN_DUAL

When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DIN phase.
FDOUT_DUAL

When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in DOUT phase.
FADDR_DUAL

When SPI1 accesses to flash or Ext_RAM, set this bit to enable 2-bm in ADDR phase.
FDIN_QUAD

When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DIN phase.
FDOUT_QUAD

When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in DOUT phase.
FADDR_QUAD

When SPI1 accesses to flash or Ext_RAM, set this bit to enable 4-bm in ADDR phase.

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data